2.5 Single-Ended-to-SSTL_2 Clock Driver (33MHz - 233MHz)

Not recommended for new designs

Features

  • Low skew, low jitter PLL clock driver 
  • 1 to 10 differential clock distribution (SSTL_2) 
  • Feedback pin for input to output synchronization 
  • PD# for power management 
  • Spread Spectrum tolerant inputs

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
95V157AG Obsolete PA48 TSSOP 48 C No Tube Availability
95V157AGI Obsolete PA48 TSSOP 48 I No Tube Availability
95V157AGIT Obsolete PA48 TSSOP 48 I No Reel Availability
95V157AGLF Obsolete PAG48 TSSOP 48 C Yes Tube Availability
95V157AGLFT Obsolete PAG48 TSSOP 48 C Yes Reel Availability
95V157AGT Obsolete PA48 TSSOP 48 C No Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
95V157A Datasheet Datasheet PDF 214 KB Nov 25, 2008
PCNs & PDNs
PDN# : CQ-15-03 Quarter PDN for Declined Market Product Discontinuation Notice PDF 542 KB May 4, 2015
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 23, 2013
PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed Product Change Notice PDF 201 KB Dec 12, 2005