28-Bit 1:2 Registered Buffer with Parity

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Features

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
74SSTUBF32865ABKG Active BKG160 CABGA 160 C Yes Tray Availability
74SSTUBF32865ABKG8 Active BKG160 CABGA 160 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
74SSTUBF32865A Datasheet Datasheet PDF 383 KB Jun 18, 2008
PCNs & PDNs
PCN# : A1604-01 Add OSET Taiwan as Alternate Assembly Product Change Notice PDF 31 KB May 1, 2016