14-Bit Configurable Registered Buffer for DDR2

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Features

  • 14-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • 50% more dynamic driver strength than standard SSTU32864
  • Supports LVCMOS switching levels on C1 and RESET# inputs
  • Low voltage operation

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
74SSTUBF32869ABKG Active BKG150 CABGA 150 C Yes Tray Availability
74SSTUBF32869ABKG8 Active BKG150 CABGA 150 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
74SSTUBF32869A Datasheet Datasheet PDF 414 KB Jan 22, 2009
PCNs & PDNs
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB Oct 20, 2013