Double the drive of the standard 97U877 device. Low skew, low jitter PLL clock driver. 1 to 5 differential clock distribution (SSTL_18)

Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
97U2A845AHLF Obsolete ADG28 CABGA 28 C Yes Tray
Availability
97U2A845AHLFT Obsolete ADG28 CABGA 28 C Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
97U2A845A Datasheet Datasheet PDF 220 KB
PCNs & PDNs
PDN# : CQ-17-05 Quarterly Market Declined PDN Product Discontinuation Notice PDF 536 KB