Low skew, low jitter PLL clock driver; 1 to 4 differential clock distribution (SSTL_18)

Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs; 
  • Auto PD when input signal is at a certain logic state

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
97ULP844AH Obsolete AD28 CABGA 28 C No Tray
Availability
97ULP844AHLF Obsolete ADG28 CABGA 28 C Yes Tray
Availability
97ULP844AHLFT Obsolete ADG28 CABGA 28 C Yes Reel
Availability
97ULP844AHT Obsolete AD28 CABGA 28 C No Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
97ULP844A datasheet Datasheet PDF 133 KB
PCNs & PDNs
PDN# : CQ-16-02 Quarter PDN for Declined Market Product Discontinuation Notice PDF 592 KB
PDN# : CQ-14-02R2 Product Discontinuation Notice PDF 549 KB
PDN# : CQ-14-02R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 545 KB
PDN# : CQ-14-02 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 544 KB
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB