28-Bit Configurable Registered Buffer for DDR2

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.

Features

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
SSTUAF32865AHLF Obsolete BKG160 CABGA 160 C Yes Tray Availability
SSTUAF32865AHLFT Obsolete BKG160 CABGA 160 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
SSTUAF32865A Datasheet Datasheet PDF 418 KB Jan 17, 2010
PCNs & PDNs
PCN# : A1604-01 Add OSET Taiwan as Alternate Assembly Product Change Notice PDF 31 KB May 1, 2016
PDN# : CQ-15-03 Quarter PDN for Declined Market Product Discontinuation Notice PDF 542 KB May 4, 2015