With system complexity growing, having two, three, or even four interface standards on a single board is not uncommon. This tip will show some examples of how to connect output buffers of one standard to input buffers of another standard.
A common question is interoperability between standards from the same family. For example, can a SSTL 2 driver be connected to a SSTL 18 receiver? Or what about a SSTL 3 driving a SSTL 18 receiver?
Let’s first look at Voltage Swings. The voltage swings are not a problem when moving from the 3.3V or 2.5V SSTL family to the 1.8V family, assuming the VREF and VTT levels are adjusted accordingly. The potential problem is with the DC voltage, in particular, the maximum VIH.
Figure 1 shows a typical SSTL Class I environment. The maximum VIH for all three families is VDDQ + 300mV. For SSTL_18, the worst case value is VDDQ(min) + 300mV = 2V. SSTL receivers are high-impedance, so all of the current will go to and come from VTT. For SSTL_18, the VTT(max) = 969mV + 40mV = 1.009V. If there is 1V across the 50Ω resistor, then the VIH specification will be violated. This would require the driver to source 20mA, which is a definite possibility. Typical SSTL drivers will deliver 8-10mA, which would suggest that SSTL_2 and SSTL_3 drivers can drive SSTL_18 receivers.
What if the driver is able to source and sink more than 20mA? In this case, the termination scheme must be changed (see Figure 2). The values of R1 and R2 must be found such that VIN never exceeds 2V (for SSTL_18). A quick application of Kirchoff’s current will yield the correct results. This is for a logic high. In general, the user should always double check the conditions for a logic low and ensure that those are within specification for the given resistor values.
For more information on these and other techniques for implementing standards in timing devices, see Application Note AN-230
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