The 87008I is a low skew, 1:8 LVCMOS/LVTTL Clock Generator. The device has 2 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/ LVTTL outputs are designed to drive 50? series or parallel terminated transmission lines. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The bank enable inputs, CLK_ENA and CLK_ENB, support enabling and disabling each bank of outputs individually. The CLK_ENA and CLK_ENB circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The 87008I is characterized to operate with the core at 3.3V or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87008I ideal for those clock applications demanding well-defined performance and repeatability.


  • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)
  • Selectable differential CLK1, nCLK1 or LVCMOS clock input
  • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • CLK0 supports the following input types: LVCMOS, LVTTL
  • Maximum output frequency: 250MHz
  • Independent bank control for ÷1 or ÷2 operation
  • Glitchless, asynchronous clock enable/disable
  • Output skew: 105ps (maximum) @ 3.3V core/3.3V output
  • Bank skew: 70ps (maximum) @ 3.3V core/3.3V output
  • 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in both standard and lead-free RoHS compliant packages


発注型名 Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete 24 I はい Tube
Obsolete 24 I はい Reel


タイトル 他の言語 分類 形式 サイズ 日付
87008I Datasheet データシート PDF 282 KB
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 製品中止通知 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 製品中止通知 PDF 537 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 95 KB
PCN# : A1509-03 Gold to Copper wire 製品変更通知 PDF 31 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 製品変更通知 PDF 361 KB
87008i IBIS モデル-IBIS ZIP 103 KB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB