Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.


  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

Product Options

注文可能な製品ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
74SSTUBF32868ABKG Obsolete CABGA 176 C 1 Tray Package Info
74SSTUBF32868ABKG8 Obsolete CABGA 176 C 1 Reel Package Info

Documentation & Downloads

タイトル 他の言語 Type 形式 サイズ 日付
74SSTUBF32868A Data Sheet Datasheet PDF 723 KB
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB