NOTICE - The following device(s) are recommended alternatives:

The 8344I is a low voltage, low skew fanout buffer and a member of the family of High Performance Clock Solutions from IDT. The 8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The 8344I is designed to translate any differential signal levels to LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. 8344I is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes.

Guaranteed output and part-to-part skew characteristics make the 8344I ideal for those clock distribution applications demanding well defined performance and repeatability.

特性

  • Twenty-four LVCMOS/LVTTL outputs, 7Ω typical output impedance
  • Two selectable differential clock input pairs for redundant clock applications
  • CLKx, nCLKx pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 100MHz
  • Translates any single-ended input signal to LVCMOS/LVTTL with resistor bias on nCLK input
  • Multiple output enable pins for disabling unused outputs in reduced fanout applications
  • Output skew: 275ps (maximum)
  • Part-to-part skew: 600ps (maximum)
  • Bank skew: 150ps (maximum)
  • Supply modes:
    Core/Output
    3.3V/3.3V
    3.3V/2.5V
    2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

产品选择

下单器件 ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete 48 I 是的 Tray
Availability
Obsolete 48 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8344I Datasheet 数据手册 PDF 254 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN 产品停产通告 PDF 560 KB
PDN# : CQ-16-02 Quarter PDN for Declined Market 产品停产通告 PDF 592 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN#: A1309-03 Additional Assembly Sources 产品变更通告 PDF 398 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 产品变更通告 PDF 472 KB
Downloads
8344I IBIS Model 模型 - IBIS ZIP 48 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB