The ICS670-02 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of IDT’s ClockBlocksTM family, the part’s zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin. The ICS670-02 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data
communications to video. By allowing off-chip feedback paths, the chip can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including functional multipliers, see the ICS527.

特性

  • Packaged in 16-pin SOIC
  • Pb (lead) free package, RoHS compliant
  • Clock inputs from 5 to 160 MHz (see page 2)
  • Patented PLL with low phase noise
  • Output clocks up to 160 MHz at 3.3 V
  • 15 selectable on-chip multipliers
  • Power down mode available
  • Low phase noise: -111 dBc/Hz at 10 kHz
  • Output enable function tri-states outputs
  • Low jitter 15 ps one sigma
  • Advanced, low power, sub-micron CMOS process
  • Operating voltage of 3.3 V or 5 V
  • Industrial temperature range available (-40 to +85°C)

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete SOIC 16 C 是的 Tube
Availability
Obsolete SOIC 16 C 是的 Reel
Availability
Not Recommended for New Designs SOIC 16 I 是的 Tube
Availability
Not Recommended for New Designs SOIC 16 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
670-02 Datasheet 数据手册 PDF 234 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers 应用文档 PDF 294 KB
PCN / PDN
PDN# : CQ-18-03 Product Discontinuance Notice 产品停产通告 PDF 218 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1309-01 Changed of Traceability Mark Format 产品变更通告 PDF 439 KB
PCN# : A1208-01R1 Gold to Copper Wire 产品变更通告 PDF 254 KB
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil 产品变更通告 PDF 223 KB
Downloads
670-02 3.3V IBIS Model 模型 - IBIS ZIP 3 KB
670-01 5.0V IBIS Model 模型 - IBIS ZIP 3 KB
670-01 3.3V IBIS Model 模型 - IBIS ZIP 3 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB