How to calculate the integer and fractional components of skew for IDTs 5P49V5901 VersaClock 5 Programmable Clock Generator device

Skew is not implemented with a parallel load of the count of the output divider as is commonly done with non-fractional divides. Instead, skew is accomplished by increasing the value of the fractional output divider for only the very first clock cycle. The divide is increased by the number of VCO cycles required to delay the completion of the first output clock cycle by the desired skew. For the second and all subsequent output cycles, hardware changes the output divider to the value for the proper steady state output frequency. To illustrate, suppose there are two output clocks defined as four cycles of FVCO/2 per FOD output clock cycle, that is N=4. OUT2 is to be delayed by 90 degrees relative to OUT1 and the power on reset phase aligns the output clocks out of reset.
 
 
The integer and fractional components of skew are calculated as follows:
 
Refer to application note AN-862 for more details. For other questions not addressed by the Knowledge Base, please submit a technical suport request.

Documents

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-862 5P49V5901 Register Programming Guide Application Note PDF 91 KB Jun 25, 2014