Use the following example for the calculations:
Jitter Attenuator Example
• Input CLK0 frequency: 25MHz
• Output Frequency: 125MHz (integer output divider)
• Output 2 Frequency: 155.52MHz (fractional output divider)
• Crystal frequency: 38.88MHz
• Crystal Doubler: Enabled
Within the device there are 3 sources of frequency error. Which of these sources may affect the output frequency depends on the configuration of the device.
1) Upper loop feedback fraction (Synth) - the upper PLL loop makes use of a Delta-Sigma Modulator (DSM) to create a feedback ratio that consists of an integer and a fractional portion. Due to the limited number of bits available to represent the fraction portion (21 bits), there will be rounding error in some cases.
2) Lower loop PFD Frequency mismatch (JA) - the Phase / Frequency Detector (PFD) circuit in the lower loop compares a pre-divided input reference frequency to the VCO frequency divided by M1.
3) Fractional Output Divider rounding (FOD) - a fractional output divider has a limited number of bits (28 bits) to represent the fractional portion of the desired output divider ratio. Because of this, rounding error may affect the output frequency.
The net error can be calculated by using the register settings to calculate the actual output frequency, based on the input and comparing it to the desired output frequency. The calculations are:
Fout_lower_calc = Fin/P * M1 /N_default (JA error)
Fout_upper_calc=Fxtal*XTAL_Doubler/(DSMInt+DSMFrac/2^21))/N_default (Synth error)
Fout2_lower_calc=Fin/P * M1 /(2*(N_Q2+ float(NFRAC_Q2)/2**28)) (JA + FOD errors)
Fout2_upper_calc=Fxtal*XTAL_Doubler/(DSMInt+DSMFrac/2^21))/ (2*(N_Q2+ float(NFRAC_Q2)/2**28)) (Synth + FOD errors)
(Fcalc-Ftarget)/Ftarget*1e9 (scale result to parts-per-billion)