How to calculate the PLL Fractional Feedback Divider for IDTs 5P49V5901 VersaClock 5 Programmable Clock Generator device

The PLL feedback divider M is composed of a 12 bit integer portion, FB_intdiv[11:0] and a 24 bit fractional portion, FB_frcdiv[23:0].
Convert FRAC(M) to hex with Eq.2 where ROUND2INT means to round to the nearest integer. The round-off error of M in ppm is the VCO frequency error in ppm.
Refer to application note AN-862 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.

Documents

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-862 5P49V5901 Register Programming Guide Application Note PDF 91 KB Jun 25, 2014