How to calculate the upper loop feedback divider for devices in the 3rd generation Universal Frequency Translator family (8T49N28X)

Use the following example for the calculations:
Jitter Attenuator Example
• Input CLK0 frequency: 25MHz
• Output Frequency: 125MHz (integer output divider)
• Output 2 Frequency: 155.52MHz (fractional output divider)
• Crystal frequency: 38.88MHz
• Crystal Doubler: Enabled
The 8T49N28X device has an upper loop (where the analog PLL and VCO reside) and a lower loop (where the DPLL resides). The upper loop feedback divider is calculated first. The feedback divider for the upper loop is the ratio between the Crystal Input frequency and the VCO frequency. If enabled, the Crystal doubler multiplies the crystal input by a factor of 2. The calculation for the upper loop feedback divider is:
UpperFBDiv= Fvco/ (Fxtal*XTAL_Doubler)
 
When mapped to the registers, the feedback divider (sometimes called the M1 divider) setting has two components:
DSMint.DSMFrac
where
DSMint = integer UpperFBDiv
DSMFrac= fraction of UpperFBDiv * 2^21, rounded to the closest integer
For the example, the crystal doubler is enabled, so the analog feedback divider is:
UpperFBDiv= Fvco/ (Fxtal*XTAL_Doubler)= 4000/(38.88*2)= 51.440329218107
DSMint=51
DSMFrac=round 0.440329218107*2^21= 923437
 
Refer to application note AN-860 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.
 

Documents

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-860 8T49N28X Frequency Programming Guide Application Note PDF 214 KB Jun 4, 2014