How to enable Memory Block programming for IDTs Time-Slot Interchanger (TSI) products

Memory block programming capability is provided to ease the initialization of the entire Connection Memory block. The feature involves 4 control bits in Control register (A[15:14] = 01): MBP (bit 9), BPD[1:0] (bit 8 and 7), BPE (bit 6). The following is a working procedure for activating Memory Block Programming. 
 
 
Once a zero-to-one transition is created on BPE bit, the entire Connection Memory block will be initialized in 2 frames (2x125μs = 250μs). The initialization process put A[15:14] = BPD[1:0], A[13:0] = 0x0000 in every single locations in Connection Memory block. By completion, the device will reset BPD[1:0] = 00. To disable the Memory Block Program feature, configure MBP = 0. In this case, the system processor needs to conduct the initialization process by writing into every location of the Connection Memory block. Refer to application note AN-852 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.

Documents

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-852 Application Considerations for Time-Slot Interchange (TSI) Products Application Note PDF 119 KB May 14, 2014