How to interface LVDS to 3.3V CML for IDT timing devices

AC coupling an LVDS signal to 3.3V CML can be accomplished using a small number of passive components. Figure 1 shows an example of LVDS clock driver driver to CML receiver interface circuit. In this example, the CML receiver is high input impedance without built-in matched load termination. For long traces between the driver and the receiver, the traces pair is treated as transmission line with controlled differential characteristic impedance Zo_diff of approximately 100 ohm. The resistor R1, R3, R4, R5 and R6 are located as close as possible to the receiver. The AC coupling capacitors C1 and C2 values will depend on the operating frequency, suggest value is ranged from 1nF to 0.1uF for the clock frequency range of 50MHz to 700 MHz. Figure 2 shows a typical steady state simulation result probed at the receiver. In this simulation, the frequency is 100MHz, and C1=C2=1nF. Figure 2 shows another example. In this example, if the receiver has built-in 100 ohm across the differential input, the board level 100 ohm is not required. See the solution below. For other questions not addressed by the Knowledge Base, please submit a technical support request.