High speed differential clock drivers require matched load termination near the differential input. The termination generates equal DC potential at the differential input when the clock signal is absent due to tri-stated outputs or floating inputs. This equal potential can cause oscillation at high frequencies which will be prevented by placing a small DC offset input voltage between CLK and nCLK. Wider DC offset input voltage provides more margin to prevent oscillation. However, setting this DC offset too wide will increase the offset between the true and complementary input signals during normal operation. Several termination examples of self oscillation prevention for various types of termination are provided below. Refer to application note AN-833 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.