How to terminate HSTL for IDT timing devices

DC termination of HSTL can be can be accomplished using a small number of passive components. High-speed transceiver logic or HSTL signaling can either be single-ended or differential with a nominal swing amplitude from 0 V to 1.5 V. The HSTL standard is defined by the JEDEC EIA/JESD8-6 standard, which specifies four classes. All four classes are similar in that they all terminate to VTT, which is defined as VDDQ/2. Refer to figure 1. IDT devices have HSTL level complaint outputs, but instead of terminating to VTT, they require a termination of 50Ω to ground. There are several advantages of terminating with 50Ω to ground. Refer to figure 2. See the solutions below. For other questions not addressed by the Knowledge Base, please submit a technical support request.