I find that my PLL will not lock properly when one of two selectable clock sources (e.g. an LVCMOS driving a differential input through an attenuator) is not selected and not active. Why can’t I tri-state or turn off the unused single ended clock?

The root cause is that with no clock source driving the input attenuator, the clock receiver sees no differential signal and the differential input buffer switches on noise.  This noise then couples internally into the PLL causing a failure to lock.  The correction is to provide at least 40mV of input offset, positive or negative, on the inverting clock input to overcome the input referred circuit noise and force the clock receiver to a stable logic state.

The details of the attenuator are as follows.  To reduce the large LVCMOS swing a source termination resistor pads the LVCMOS output impedance to 50 ohms and input transmission line is terminated in a 100ohm – 100ohm voltage divider at the clock receiver input and powered by the clock receiver VCC to reduce the LVCMOS swing in half, bias the received clock logic threshold to VCC/2 and terminate the clock line.  The inverting clock input is biased with a typically 1k-1k voltage divider to provide the VCC/2 slicer threshold for the attenuated LVCMOS clock at the non-inverting clock input.

The origin of the zero input offset is understood by looking at both the external resistors and internal resistors in the clock receiver.  The 50 ohm impedance level of the 100ohm-100ohm attenuator is so low that it is not loaded by the internal 51k pull down resistor.  Therefore the non-inverting terminal is biased to VCC/2.  On the inverting terminal, the 1k-1k divider is paralleled with an internal 51k-51k voltage divider so the inverting terminal is also biased to VCC/2.

The solution is to introduce a +40mV or -40mV offset into the inverting input external voltage divider.  Offsets larger than this will also work to suppress noise switching, but the offset does degrade input clock noise margin.  It also can change the duty cycle of the input clock, but PLLs only look at the rising clock edge for timing information so duty cycle is not an issue.

Example: VCC = 3.3V, change the 1k-1k voltage divider to 1k-953 or 953-1k for a +/- 40mV offset.  With 5% resistors, use 910 instead of 953, but the offset is then +/- 77mV.

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