What are the PLL pre-divider options for IDTs 5P49V5901 VersaClock 5 Programmable Clock Generator device?

The reference presented to the fractional PLL can be either directly connected, divided by two or divided by the any value from
the range of three to 127 as set in the register Ref_Div[6:0]. The phase detector of the PLL has a maximum frequency of 50
MHz, therefore the default is to bypass the pre-divider by setting Bypss_prediv = 1. For the functionality of Sel_prediv2 and
bypss_prediv bits, see the figure below. Refer to application note AN-862 fro more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.
 

Documents

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-862 5P49V5901 Register Programming Guide Application Note PDF 91 KB Jun 25, 2014