Traditional HCSL termination uses a 50Ω resistor to ground at the end of the PCB trace. Later, another method was introduced, placing the 50Ω to ground near the driver. This is called “Source Termination” and allows for the clock to pass through connectors that can be unplugged while the circuit is active (hot swapping). LP-HCSL has its termination at the driver side by definition, and it can work with end terminations. This setup is referred to as double termination (more on this in a moment). Source termination versus end termination makes no difference to the receiver.
The termination resistors (RS) are now in series with the clock line, near the driver. The driver itself is designed to have 17Ω
output impedance so it requires another 33Ω to match 50Ω PCB traces. The schematic on the right has the termination resistors
integrated so no external components are needed to drive 50Ω PCB traces.
Traditional HCSL doesn't use the driver itself as part of the termination. Besides the 50Ω termination resistor, traditional HCSL
needs an additional 33Ω series resistor to avoid a reflection and ringing between the driver and the 50Ω terminated trace. The
LP-HCSL concept combines the main termination and ringing avoidance in the same 33Ω series resistor, reducing the parts
Certain applications use 85Ω differential traces (or 42.5Ω single ended). For these applications, we recommend RS=27Ω. IDT
also offers clocks with the 27Ω RS integrated for 85Ω systems.
Double Termination: Certain receivers may have a 100Ω differential termination resistor of in the chip. These receivers are
usually more generic, can handle a wide range of amplitudes and common-mode voltages, and may require AC coupling of the
clock signals. LP-HCSL drivers can readily drive double terminations. Having termination resistors at both the source and
receiver lowers the amplitude to about 400mVpp at each pin (800mVpp differential). Usually it is not a problem for this type
receiver to work with the smaller amplitudes. The 400mVpp (800mVpp differential) level even exceeds the 150mVpp (300mVpp
differential) input swing spec for PCIe reference clocks.
For other questions not addressed by the knowledge base, please submit a technical support request.