The NC pin between pins #1 and #3, is a duplicate of the circuitry in pin #1 with a greater than 8 Mega ohm resistance pulled up to 3.3V. The next subsequent stage is isolated with a high impedance so that there is no internal effect or possible damage by connection of either pin #1 or #3 to each other or to ground.
This characteristic is to accommodate similar parts by a competitor who places the Enable-Disable input on pin #2. All complementary output XU configurations (LVDS, LVPECL, & HCSL) have an option for Pin #2 E/D, instead of Pin #1.
For other questions not addressed by the knowledge base, please submit a technical support request.