The 9DBL0653 Zero-Delay/Fanout buffer is a low-power high-performance member of Reneas' Full-Featured PCIe family. The buffer supports PCIe Gen1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0651.
 
For information regarding evaluation boards and material, please contact your local sales representative.
 

Features

  • Loss of Signal (LOS) output; supports fault tolerant systems
  • Supports PCIe Gen1–5 CC and IR in fanout mode
  • Supports PCIe Gen1–5 CC in High Bandwidth ZDB mode
  • Direct connection to 85Ω transmission lines; saves 24 resistors compared to standard PCIe devices
  • Spread spectrum tolerant; allows reduction of EMI
  • Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Easy AC-coupling to other logic families, see application note AN-891.
  • Space saving 5 × 5 mm 40-VFQFPN; minimal board space

Product Options

Orderable Part ID Part Status Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
Active 40 I 85 Tray
Availability
Notice: there are one or more orderable products that are not available in your region. For questions, contact your local sales representative.

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DBL02x3-04x3-06x3-08x3 Family Datasheet Datasheet PDF 473 KB
User Guides & Manuals
Timing Products for NXP (Freescale) i.MX 简体中文 Guide PDF 321 KB
Application Notes & White Papers
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Downloads
9DBL06P1 IBIS Model Model - IBIS ZIP 118 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
PCI Express Timing Solutions Overview Overview PDF 275 KB
9DBL06xx Reference Schematic Schematic PDF 118 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB