The 8T39S10I is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by single-ended clock when crystal is bypassed.The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open circuit or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

Features

  • Two differential reference clock input pairs
  • Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Maximum Output Frequency
    • LVPECL - 2GHz
    • LVDS - 2GHz
    • HCSL - 250MHz
    • LVCMOS - 250MHz
  • Two banks, each has five differential output pairs that can be configured as LVPECL or LVDS or HCSL
  • One single-ended reference output with synchronous enable to avoid clock glitch
  • Output skew: (Bank A and Bank B at the same output level: 70ps (max)
  • Part-to-part skew: 250ps (max)
  • Additive RMS phase jitter: 0.153ps (typical)
  • Supply voltage modes:
    • VDD/VDDO
    • 3.3V/3.3V
    • 3.3V/2.5V
    • 2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

Product Options

Orderable Part ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete 48 I Yes Tray
Availability
Obsolete 48 I Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8T39S10I Data Sheet Datasheet PDF 1.08 MB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PDN# : CQ-17-02R1 Quarterly Market Declined PDN (revision1) Product Discontinuation Notice PDF 647 KB
PDN# : CQ-17-02 Quarterly Market Declined PDN Product Discontinuation Notice PDF 898 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB