The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The 8735BI-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.

Features

  • One differential 3.3V LVPECL output pair, one differential feedback output pair
  • Differential CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL
  • Output frequency range: 31.25MHz to 700MHz
  • Input frequency range: 31.25MHz to 700MHz
  • VCO range: 250MHz to 700MHz
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
  • External feedback for “zero delay” clock regeneration with configurable frequencies
  • Cycle-to-cycle jitter: 50ps (maximum)
  • 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in RoHS compliant package

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
8735BKI-21LF Active VFQFPN 32 I 1 Tray Package Info
Availability
8735BKI-21LFT Active VFQFPN 32 I 1 Reel Package Info
Availability
8735BMI-21LF Active SOIC 20 I 1 Tube Package Info
Availability
8735BMI-21LFT Active SOIC 20 I 1 Reel Package Info
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8735BI-21 Datasheet Datasheet PDF 527 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB