Any component in a signal chain has some amount of noise at its output that is generated internally (not including the contribution due to the external reference noise at the input). It is useful to measure the phase noise at the output of a device in such a way that the phase noise of any external source is canceled out. The phase noise so measured is specified as the additive phase noise of the device. It is the amount of phase noise that the device (clock buffer in our case) adds to the signal chain. IDT clock buffers have ultra low additive phase jitter thereby allowing system designers to distribute multiple copies of a clean clock to other devices on their system. The clock signal integrity is maintained thereby eliminating the need for additional jitter cleaning components.  Refer to application note AN-804 for more details. For questions not answered by the Knowledge Base, please submit a technical support request.


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Application Notes & White Papers
AN-804 IDT Clock Buffers Offer Low Additive Phase Jitter Application Note PDF 246 KB