The 8714004I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for "zero delay" clock regeneration. In PCI Express® and Ethernet applications, 100MHz and 125MHz are the most commonly used reference clock frequencies and each of the eight output pairs can be independently set for either 100MHz or 125MHz. With an output frequency range of 98MHz to 165MHz, the device is also suitable for use in a variety of other applications such as Fibre Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS Input/Output pair is useful in backplane applications when the reference clock can either be local (on the same board as the 8714004I) or remote via a backplane connector. In output mode, an input from a local reference clock applied to the CLK/nCLK input pins is translated to M-LVDS and driven out to the MLVDS/nMLVDS pins. In input mode, the internal M-LVDS driver is placed in Hi-Z state using the OE_MLVDS pin and MLVDS/nMLVDS pin then becomes an input (e.g. from a backplane). The 8714004I uses very low phase noise FemtoClock technology, thus making it ideal for such applications as PCI Express® Generation 1 and 2 as well as for Gigabit Ethernet, Fibre Channel, and 10 Gigabit Ethernet. It is packaged in a 40-VFQFN package (6mm x 6mm).

特長

  • Four 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications
  • One differential clock input pair CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL
  • One M-LVDS I/O pair (MLVDS/nMLVDS)
  • Output frequency range: 98MHz - 165MHz
  • Input frequency range: 19.6MHz - 165MHz
  • VCO range: 490MHz - 660MHz
  • PCI Express® (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
  • External feedback for "zero delay" clock regeneration
  • RMS phase jitter @ 125MHz (1.875MHz – 20MHz): 0.62ps (typical)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete VFQFPN 40 I はい Tray
Availability
Obsolete VFQFPN 40 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8714004I Datasheet データシート PDF 536 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN 製品中止通知 PDF 560 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 50 KB
PCN# : A1309-01 Changed of Traceability Mark Format 製品変更通知 PDF 439 KB
その他資料
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB