The 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

特性

  • Eight low skew, low additive jitter LVPECL output pairs
  • Two selectable, differential clock input pairs
  • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 2GHz
  • LVCMOS interface levels for the control input (input select)
  • Output skew: 28ps (typical)
  • Propagation delay: 410ps (maximum)
  • Low additive phase jitter, RMS: 54.1fs (maximum) (fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
  • Full 3.3V and 2.5V supply voltage
  • Maximum device current consumption (IEE): 141mA
  • Available in lead-free (RoHS 6), 28-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 28 I 是的 Tray
Availability
Active VFQFPN 28 I 是的 Reel
Availability
Active VFQFPN 28 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8SLVP1208 Datasheet 数据手册 PDF 817 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 产品变更通告 PDF 583 KB
Downloads
8SLVP1208I IBIS Model 模型 - IBIS ZIP 77 KB
其他
RF Timing Family Product Overview 概览 PDF 464 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
High-Performance, Low-Phase Noise Clocks Buffers product brief 产品简述 PDF 378 KB