The 651S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 651S has best in class Additive Phase Jitter of sub 50 fsec.

特性

  • Low additive phase jitter RMS: 50 fs
  • Extremely low skew outputs (50 ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
  • Input / Output clock frequency up to 200 MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating Voltages: 1.8 V to 3.3 V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active COL 8 I 是的 Cut Tape
Availability
Active COL 8 I 是的 Reel
Availability
Active SOIC 8 I 是的 Tube
Availability
Active SOIC 8 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
651S Datasheet 数据手册 PDF 305 KB
应用指南 &白皮书
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
PCN / PDN
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets 产品变更通告 PDF 268 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB