The 8T39S11A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock.The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

特性

  • Two differential reference clock input pairs
  • Differential input pairs can accept the following differential input
    levels: LVPECL, LVDS, HCSL, HSTL or Single Ended
  • Crystal Input accepts 10MHz to 40MHz Crystal or Single Ended Clock
  • Maximum Output Frequency
    LVPECL   - 2GHz
    LVDS       - 2GHz
    HCSL       - 250MHz
    LVCMOS - 250MHz
  • Two banks, each has five differential output pairs that can be
    configured as LVPECL or LVDS or HCSL
  • One single-ended reference output with synchronous enable to avoid clock glitch
  • Output skew: 80ps (maximum)
    (Bank A and Bank B at the same output level)
  • Part-to-part skew: 200ps (typical)
  • Additive RMS phase jitter @ 156.25MHz:
    5.6fs RMS (10kHz - 1 MHz), typical @ 3.3V/ 3.3V
    34.7fs RMS (12kHz - 20MHz), typical @ 3.3V/ 3.3V
  • Supply voltage modes:
    VDD/VDDO
    3.3V/3.3V
    3.3V/2.5V
    2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging​

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 48 I 是的 Tray
Availability
Active VFQFPN 48 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8T39S11A Datasheet 数据手册 PDF 945 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB