Ron Wade
Datacenter Timing System Architect

Welcome to the next topic for Integrated Device Technology’s PCI Express® Timing Blog. A lot has happened since our first issue and this topic is appropriately named “Future Proofing.” When we talk about future-proofing with respect to system design, we refer to the attempt to re-use a design for more than one product generation. The phrase sometimes means anticipating certain technology developments so that one’s project is not made obsolete (or at least not too soon). That said, some things cannot be anticipated.

In a prior blog post, Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications, I mentioned that PCIe Gen5 was moving to release in a much shorter period than PCIe Gen4 had.  Since then, the PCI SIG released version 1.0 of the PCIe Gen5 specification on May 28, 2019, and is now engaged in PCIe Gen6 work! 

So what does this have to do with future proofing? When IDT designs PCIe clock chips, we always attempt to aim ahead of the current specifications for performance. Several benefits accrue from this approach, which allows use of our PCIe clock chips for more than one PCIe generation. Both IDT and our customers share in these benefits:

  1. Customers get improved performance margin for today’s systems and can continue using the parts for next-generation designs. This saves procurement, qualification and design time.
  2. IDT is able to increase lifetime volumes on the clock chips, which improves reliability and brings about additional supply-chain benefits, which also accrue to our customers. 

Figure 1 shows a timeline of PCI Express development since its beginning. The top half of the timeline lists the release dates for each PCIe generation specification. The bottom half shows the availability dates of IDT-compliant clocks for each generation. You can see that in general, the clocks were available before the finalization of specifications. The exception to date has been PCIe Gen1, when the whole industry was bringing an entirely new technology ecosystem to market.  
 

Figure 1 PCI Specification Release versus IDT PCIe Clock Availability

The time between the release of a PCI Express specification and deployment of compliant systems can be significant, years in some cases. Looking at Figure 1, IDT had PCIe Gen4-compliant parts in late 2015, the PCIe Gen4 specification was released in late 2017, and PCIe Gen4 systems began shipping in mid-2019. When we have devices that are compliant to an unreleased specification, we note that they are ready for the upcoming generation. The devices we introduced in late 2015 were described as Gen4-ready.

Similarly, IDT introduced PCIe devices last spring that were noted as Gen5-ready.  Now, we have officially updated the documentation of several device families to indicate official Gen5 compliance. We’ve prepared a one-page PCIe Timing overview so you can see the performance specifications at a glance. 

Does IDT have Gen6-ready devices today? Time will tell as we wait for the work to be complete on that specification. But we are certainly looking to the future. Thanks for reading.

Visit idt.com/pcietiming to see the complete PCIe timing portfolio and select the clock generator or buffer that best fits your next design.
 

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