NOTICE - The following device(s) are recommended alternatives:
The IDT5T9110 is a 2.5V PLL differential clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5T9110 has six differential programmable skew outputs in six banks, including a dedicated differential feedback. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality of 2 or 4. The IDT5T9110 features a user-selectable, single-ended or differential input to six differential outputs. The differential clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL
outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The differential outputs can be synchronously enabled/disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF.


  • 2.5 VDD
  • 6 pairs of programmable skew outputs
  • Low skew: 100ps all outputs
  • Selectable positive or negative edge synchronization
  • Tolerant to spread spectrum input clock
  • Synchronous output enable
  • Selectable reference input
  • Input frequency: 4.17MHz to 250MHz
  • Output frequency: 12.5MHz to 250MHz
  • 1.8V / 2.5V LVTTL: up to 250MHz
  • HSTL / eHSTL: up to 250MHz
  • Hot insertable and over-voltage tolerant inputs
  • 3-level inputs for skew control
  • 3-level inputs for selectable interface
  • 3-level inputs for divide selection multiply/divide ratios of (1-6, 8, 10, 12) / (2, 4)
  • Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface
  • Selectable differential or single-ended inputs and six differential outputs
  • PLL bypass for DC testing
  • External differential feedback, internal loop filter
  • Low Jitter: <75ps cycle-to-cycle
  • Power-down mode
  • Lock indicator

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
5T9110BBGI Obsolete PBGA 144 I Yes Tray Package Info

Documentation & Downloads

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-237: PLL Lock Indicator Application Note PDF 250 KB
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB