DDR Zero Delay Clock Buffer
Features
- Low skew, low jitter PLL clock driver
- I2C for functional and output control
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- 3.3V tolerant CLK_INT input
DDR Zero Delay Clock Buffer
Title | Other Languages | Type | Format | File Size | Date | |
---|---|---|---|---|---|---|
93722 IBIS Model | – | Model - IBIS | ZIP | 7 KB |