NOTICE - The following device(s) are recommended alternatives:

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.

Features

  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
SSTUAF32866CHLF Obsolete CABGA 96 C Yes Tray Package Info
Availability
SSTUAF32866CHLFT Obsolete CABGA 96 C Yes Reel Package Info
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
SSTUAF32866C Datasheet Datasheet PDF 662 KB