The Renesas DPLLs (Digital PLLs) for IEEE1588 and synchronous Ethernet are designed for synchronization over packet switched networks. For IEEE1588 applications the embedded DCOs (Digitally Controlled Oscillators) can be used as low-jitter synthesizers for IEEE1588 clock recovery algorithms. For synchronous Ethernet applications the DPLLs comply with ITU-T recommendations for EECs (synchronous Ethernet Equipment Clocks); these devices also comply with SONET/SDH, PDH and TDM synchronization requirements. The Renesas DPLLs can be switched between IEEE1588 DCO and SyncE modes; and they provide capabilities such as selectable loop filters, holdover, hitless reference switching, phase slope limiting and clock redundancy.
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About IEEE 1588
IEEE 1588 is a precision time protocol (PTP) used to synchronize clocks throughout a computer network. On a local area network, it achieves clock accuracy in the sub-microsecond range, making it suitable for measurement and control systems. The IEEE 1588 standard defines a master-slave architecture for clock distribution, consisting of one or more network segments, and one or more clocks. Renesas addresses IEEE 1588 clocking needs with an industry-leading portfolio of high-performance solutions.
About Synchronous Ethernet (SyncE)
Synchronous Ethernet is an ITU-T standard for computer networking that defines how clock signals are transferred over the Ethernet physical layer. The purpose of synchronous Ethernet is to provide a synchronization signal to various resources over a network. The synchronous Ethernet signal is transmitted over the Ethernet physical layer and should be traceable to an external clock. Applications include routers, multi-service switching platforms, PON (Passive Optical Network) and DSLAMs (Digital Subscriber Line Access Multiplexers). As the only supplier with all of the different timing components to provide complete solutions, Renesas is uniquely positioned to meet the needs of communication equipment suppliers and offer compelling solutions for all timing fabric architectures.