The 82P33931-1 Synchronization System for IEEE 1588 is comprised of software and hardware designed to meet the needs of IEEE 1588 slave clock and master clock applications. The system includes Precision Time Protocol (PTP) stack software (Stack) and clock recovery servo software (Servo) that runs on an external processor; and Synchronization Management Unit (SMU) hardware.

The included PTP stack is IEEE 1588-2008 compliant and is used to control the exchange of messages between IEEE 1588 masters and slaves.The Servo recovers accurate and stable electrical synchronization signals from packet based references generated by IEEE 1588 masters. The Servo is capable of filtering the effects of Packet Delay Variation (PDV) often present in IEEE 1588 unaware networks.

The SMU hardware provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

For more information or to request documentation, please contact your local IDT sales representative.

Features

  • Includes IEEE 1588-2008 compliant protocol stack, clock recovery servo software, and Synchronization Management Unit (SMU) hardware
  • Implements ITU-T Telecom Profiles
  • Operates as IEEE 1588 / PTP slave or master
  • Recovers accurate and stable synchronization signals from packet based IEEE 1588 / PTP master
  • Reference trackers filter packet synchronization noise from IEEE 1588 unaware networks
  • PTP clocks comply with ITU-T G.8273.2 and G.8263
  • Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • System-wide precise 1PPS (Pulse Per Second) time of day alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • 144 pin CABGA package

Product Options

Orderable Part ID Part Status Pkg. Code Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
82P33931-1BAG Active BAG144 C Yes Tray
Availability
82P33931-1BAG8 Active BAG144 C Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
82P33931-1 Datasheet Datasheet PDF 238 KB
Application Notes & White Papers
Procedure to Program Clock Phase Skew of 82P338XX_9XX_r6 Application Note PDF 613 KB
SyncE Wander Testing for Marvell 88X3340P and IDT 82P33731 White Paper White Paper PDF 610 KB
AN-888 SMU for IEEE 1588 and Synchronous Ethernet 82P338xx/339xx Register Map Application Note PDF 845 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 324 KB
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs Application Note PDF 300 KB
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 164 KB
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 249 KB
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs Application Note PDF 606 KB
ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
PCNs & PDNs
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages Product Change Notice PDF 93 KB
Downloads
Timing Commander Installer (v1.15.0.27471) Software ZIP 19.57 MB
82P33931-1 BSDL File Model - BSDL BSD 20 KB
82P33x31 Timing Commander Personality Software TCP 4.00 MB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
Timing Fabric for Next Generation Communications Equipment Overview 日本語, 简体中文 Overview PDF 1.31 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
Timing Fabric for Communications Equipment Overview Overview PDF 263 KB

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