The 8A34013 Line Card Synchronizer for IEEE 1588 regenerates and distributes ultra-low jitter; precision timing signals that are locked to IEEE 1588 and Synchronous Ethernet (SyncE) reference sources elsewhere in a system. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media that introduce clock propagation delays. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 TSUs in a system. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

Features

  • Four independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • IEEE 1588 Support:
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

Product Options

Orderable Part ID Part Status Temp. Range Carrier Type Buy Sample
Active -40 to 85°C Reel
Availability
Active -40 to 85°C Reel
Availability
Active -40 to 85°C Tray
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8A34013 Datasheet Datasheet PDF 1.93 MB
8A3xxxx Firmware Version v4.8.7 Errata Notice Errata PDF 44 KB
8A3xxxx Family Errata (Rev B with Update v4.7) Errata PDF 127 KB
User Guides & Manuals
8A3xxxx Family Programming Guide (v4.8.7) Guide PDF 2.33 MB
8A3xxxx Firmware Version 4.8.7 Release Notes Guide PDF 101 KB
8A3xxxx Family Programming Guide (v4.8) Guide PDF 3.60 MB
8A34xxx 48QFN EVK User Manual Manual - Eval Board PDF 1.99 MB
ClockMatrix GUI Step-by-Step User Guide Guide PDF 4.98 MB
Application Notes & White Papers
Aligning 1PPS Clocks in Larger Chassis Systems Application Note PDF 1.62 MB
ClockMatrix: Methods for Changing DPLL Settings during a Reference Switch Application Note PDF 354 KB
AN-807 Recommended Crystal Oscillators for Network Synchronization Application Note PDF 148 KB
AN-1010 ClockMatrix Time-to-Digital Converter Application Note PDF 1.57 MB
Using a Frame or Sync Pulse Input for Clock Alignment Application Note PDF 1.57 MB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 Application Note PDF 390 KB
Translating Non-Integer Frequencies with ClockMatrix Application Note PDF 880 KB
Auto-Alignment of Outputs Application Note PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback Application Note PDF 155 KB
ClockMatrix Firmware Update through Serial Port and EEPROM v1.0 Application Note PDF 739 KB
AN-1033 Delay Variation Measurement and Compensation Application Note PDF 633 KB
AN-1034 Minimizing Backplane Signal Usage Application Note PDF 566 KB
AN-1031 Time Alignment Background in Wireless Infrastructure Application Note PDF 479 KB
AN-1032 Time-of-Day Within an Ideal Chassis-Based System Application Note PDF 442 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment Application Note PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy Application Note PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 324 KB
PCNs & PDNs
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 Product Change Notice PDF 301 KB
PCN# : TP1906-05 Correct System APLL Loss-of-Lock Issue Product Change Notice PDF 123 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products Product Change Notice PDF 435 KB
Downloads
Timing Commander Installer (v1.16.3) Software ZIP 19.85 MB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.1, FWv4.8.7) Software TCP 46.94 MB
ClockMatrix Register Header Files v4.8.7 Software ZIP 278 KB
8A340xx ClockMatrix IBIS Model Model - IBIS ZIP 2.40 MB
8A34013 BSDL Model Model - BSDL ZIP 2 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 Software ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 Software ZIP 177 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
8A3x0xx Schematic Checklist (v1.22) Miscellaneous XLSX 328 KB
ClockMatrix Family Overview Overview PDF 241 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB