The 8A34046 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) and Optical Transport Network (OTN) is a highly integrated timing device with four Digital PLL (DPLL) channels and four Digitally Controlled Oscillator (DCO) channels. The device integrates the timing blocks necessary to implement the SETS function as described in ITU-T G.8264.
The 8A34046 DPLL channels can be configured to comply with ITU-T G.8262 and G.8262.1 or as jitter attenuators; they can also be configured as DCOs. The DCO channels can be connected to a DPLL channel to supply additional outputs and frequencies for that DPLL; alternatively they can be controlled by external software or they can free run based on the local oscillator. The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
- Four independent Digital PLLs (DPLLs) and four independent Digitally Controlled Oscillators (DCOs)
- DPLLs comply with ITU-T G.8262 and G.8262.1 for SyncE and OTN
- DPLLs lock to any frequency from 1kHz to 1GHz
- DPLLs / DCOs generate any frequency from 0.5Hz to 1GHz
- Jitter output below 150fs RMS (typical)
- Supports up to 4 differential; or 8 single-ended reference clock inputs
- Supports up to 12 differential outputs; or 24 LVCMOS outputs
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
- Serial processor ports support 1MHz I2C or 50MHz SPI
- The device can configure itself automatically after reset via:
- Internal Customer-programmable One-Time Programmable memory
- Standard external I2C EPROM via separate I2C Master Port