The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 167 MHz and supports all SERDES clock frequencies for Freescale QorIQ CPUs.


  • 4 - low power differential output pairs
  • Individual OE# control of each output pair
  • Low power differential outputs
  • Power down mode when all OE# are high
  • Industrial temperature range
  • 20-pin MLF
  • Output cycle-cycle jitter <15 ps additive
  • Output to Output skew: <50 ps
  • PCIe Gen3 addtive phasejitter <0.3 ps rms
  • 10.3125G / 64 additive phase jitter <100 fs rms

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
6V31021NLGI Active NLG20P1 VFQFPN 20 I Yes Tube
6V31021NLGI8 Active NLG20P1 VFQFPN 20 I Yes Reel

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
6V31021 Datasheet Datasheet PDF 90 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB