The 9DBL0242 2-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0242 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.
For information regarding evaluation boards and material, please contact your local sales representative.
- Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)
- PCIe Gen5 CC jitter <150fs RMS (High-BW ZDB Mode)
- 2 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
- Direct connection to 100Ω transmission lines
- Dedicated OE# pin for each output
- Spread Spectrum tolerant
- Pin or SMBus configuration
- 3 selectable SMBus addresses
- SMBus interface not required for device operation
- Easy AC-coupling to other logic families, see application note AN-891.
- Space saving 24-pin 4 × 4 mm VFQFPN