The 9ZML1255 is a second generation of enhanced performance DB1200ZL derivative. The device features both PLL and Bypass mode for flexibility. The PLL has a low noise PLL that can be used as a PCIe clock jitter cleaner. The device supports PCIe Gen1–5 and more complex architecture like SRIS and SRNS clocking. 9ZML1255 also features an SMBus Write Lockout pin for increased device and system security.
 
For information regarding evaluation boards and material, please contact your local IDT sales representative.
 

Features

  • PLL or Bypass Mode; PLL can dejitter incoming clock
  • PCIe Gen1-5 compliant in PLL mode
  • PCIe Gen1-5 compliant in Bypass mode
  • Supports PCIe SRIS and SRNS clocking
  • UPI/QPI support
  • LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
  • 12 OE# pins; hardware control of each output
  • Spread Spectrum tolerant; allows reduction of EMI
  • 9 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Pin/SMBus selectable selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Easy AC-coupling to other output logic like LVPECL/LVDS; see IDT application note AN-891.
  • 10 x 10 mm 72-QFN package

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Package Buy Sample
9ZML1255AKILF Active VFQFPN 72 I 85 Tray Package Info
Availability
9ZML1255AKILFT Active VFQFPN 72 I 85 Reel Package Info
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZML1245-1255-1256 Family Datasheet Datasheet PDF 465 KB
Application Notes & White Papers
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Other
PCI Express Timing Solutions Overview Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB