The 9ZML1256 is a second generation of enhanced performance DB1200ZL derivative. The device features both PLL and Bypass mode for flexibility. The PLL has a low noise PLL that can be used as a PCIe clock jitter cleaner. The device supports PCIe Gen1–5 and more complex architecture like SRIS and SRNS clocking.
For information regarding evaluation boards and material, please contact your local IDT sales representative.
- SMBus write lock pin, increases system security
- PLL or Bypass Mode; PLL can dejitter incoming clock
- PCIe Gen1–5 compliant in PLL mode
- PCIe Gen1–5 compliant in Bypass mode
- Supports PCIe SRIS and SRNS clocking
- UPI/QPI support
- LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
- 12 OE# pins; hardware control of each output
- Spread spectrum tolerant; allows reduction of EMI
- 3 selectable SMBus addresses; multiple devices can share same SMBus segment
- Pin/SMBus selectable selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Easy AC-coupling to other output logic like LVPECL/LVDS; see IDT application note AN-891.
- 10 × 10 mm 72-QFN package