The 9ZX21901D is a second generation DB1900Z differential buffer for Intel Purley and newer platforms. The part is backwards compatible to the 9ZX21901C while offering much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. In bypass mode, the 9ZX21901D can provide outputs up to 400MHz. 

Features

  • 19 HCSL output pairs
  • Fixed feedback path
  • Phase jitter: PCIe Gen4 < 0.5ps rms
  • Phase jitter: UPI 9.6GT/s < 0.1ps rms
  • PLL or bypass mode; PLL can dejitter incoming clock
  • 9 selectable SMBus Addresses
  • 8 dedicated OE# pins
  • 100MHz or 133MHz PLL mode; legacy QPI support
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible
  • SMBus interface
  • 10 × 10 mm 72-QFN package

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
9ZX21901DKLF Active VFQFPN 72 C Yes Tray Package Info
Availability
9ZX21901DKLFT Active VFQFPN 72 C Yes Reel Package Info
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZX21901D Datasheet Datasheet PDF 307 KB
Application Notes & White Papers
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 137 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Downloads
9ZX21901D IBIS Model Model - IBIS ZIP 12 KB
Other
PCI Express Timing Solutions Overview Overview PDF 275 KB
9ZX21901 Reference Schematic Schematic PDF 25 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB