The 85314I-01 is a low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL Fanout Buffer.The 85314I-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standarddifferential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clockenable pin. Guaranteed output and part-to-part skew characteristics make the 85314I-01 ideal for those applications demanding well defined performance and repeatability.

Features

  • 5 differential 2.5V/3.3V LVPECL outputs
  • Selectable differential CLK0, nCLK0 or LVCMOS inputs
  • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 700MHz
  • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
  • Output skew: 30ps (maximum), TSSOP package 50ps (maximum), SOIC package
  • Part-to-part skew: 350ps (maximum)
  • Propagation delay: 1.8ns (maximum)
  • RMS phase jitter @ 155.52MHz (12kHz - 20MHz): 0.05ps (typical)
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS-compliant package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
85314BGI-01LF Active PGG20 TSSOP 20 I Yes Tube
Availability
85314BGI-01LFT Active PGG20 TSSOP 20 I Yes Reel
Availability
85314BMI-01LF Active PSG20 SOIC 20 I Yes Tube
Availability
85314BMI-01LFT Active PSG20 SOIC 20 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
85314I-01 Datasheet Datasheet PDF 366 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Software & Tools

Title Other Languages Type Format File Size Date
85314i-01 IBIS Model Model - IBIS ZIP 81 KB