The 854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS), the 854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100?. The 854104 accepts a differential input level and translates it to LVDS output levels. Guaranteed output and part-to-part skew characteristics make the 854104 ideal for those applications demanding well defined performance and repeatability.

Features

  • Four differential LVDS output pairs
  • One differential clock input pair
  • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Each output has an individual OE control
  • Maximum output frequency: 700MHz
  • Translates differential input signals to LVDS levels
  • Additive phase jitter, RMS: 0.232ps (typical)
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 350ps (maximum)
  • Propagation delay: 1.3ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) packages

Product Options

Orderable Part ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Last Time Buy 16 C Yes Tube
Availability
Last Time Buy 16 C Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
ICS854104 Data Sheet Datasheet PDF 639 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8) Product Discontinuation Notice PDF 743 KB
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers Product Discontinuation Notice PDF 715 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : TB1403-01 Changed in Carrier Tape, Plastic Reel and Quantity per Reel on TSSOP-14, TSSOP-16 Product Change Notice PDF 663 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
Downloads
ICS854104 IBIS Model Model - IBIS ZIP 33 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB