The 8V34S208 is a differential 1:8 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal distribution. Controlled by the input mode selection pin, the differential input stages accept both rectangular or sinusoidal signals. The 8V34S208 also provides level translated LVCMOS/LVTTL outputs which are copies of the individual differential inputs CLKA and CLKB. The propagation delay of the device is very low, providing an ideal solution for clock distribution circuits with tight phase alignment requirements. The multiplexer select pin (SEL) allows to select one out of two input signals, which is copied to the four differential outputs.

 

Features

  • Designed for 1PPS, 2kHz, 8kHz and 10MHz GPS clock signal
    distribution
  • High speed 1:8 LVDS fanout buffer
  • Eight differential LVDS output pairs
  • 2:1 input multiplexer
  • Two selectable differential inputs accept LVDS and LVPECL
    signals
  • Accepts rectangular and sinusoidal input signals
  • Two input monitoring outputs (LVCMOS)
  • Max output frequency: 250 MHz
  • Additive RMS phase jitter:
    118fs (typical) at 100Mhz (12k-20Mhz)
  • Part-to-part skew: 250ps (maximum)
  • Propagation delay: 325ps (typical), LVDS output
  • Full 2.5V and 3.3V voltage supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free 32-lead VFQFN (RoHS 6/6) packaging

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8V34S208NLGI Last Time Buy NLG32P1 VFQFPN 32 I Yes Tray
Availability
8V34S208NLGI8 Last Time Buy NLG32P1 VFQFPN 32 I Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8V34S208 Data Sheet Datasheet PDF 753 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PDN#: CQ-19-04 Product Discontinuance Notice Product Discontinuation Notice PDF 1010 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Boards & Kits