The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock Generator. The 8732-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended clock input accepts LVCMOS or LVTTL input levels. The 8732-01 has a fully integrated PLL along with frequency configurable outputs. An external feedbackinput and outputs regenerate clocks with "zero delay". The 8732-01 has multiple divide select pins for each bank of outputs along with 3 independent feedback divide select pins allowing the 8732-01 to function both as a frequency multiplier and divider. The PLL_SEL input can be usedto bypass the PLL for test and system debug purposes.In bypass mode, the input clock is routed around the PLLand into the internal output dividers.


  • Ten differential 3.3V LVPECL outputs
  • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs
  • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • CLK1 accepts the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 350MHz
  • VCO range: 250MHz to 700MHz
  • External feedback for "zero delay" clock regeneration with configurable frequencies
  • Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum) CLK1, 80ps (maximum)
  • Output skew: 150ps (maximum)
  • Static phase offset: -150ps to 150ps
  • Lead-Free package fully RoHS compliant

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
8732AY-01LF Obsolete TQFP 52 C Yes Tray Package Info
8732AY-01LFT Obsolete TQFP 52 C Yes Reel Package Info

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8732-01 Datasheet Datasheet PDF 298 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN Product Discontinuation Notice PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN Product Discontinuation Notice PDF 537 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB
8732-01 IBIS Model Model - IBIS ZIP 27 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB