The ClockMatrix family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. 

They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

Key features include:

  • Flexibility – PLL channels are individually configurable as synthesizer, jitter attenuator, or DCO
  • Integration – up to 8 DPLLs and 12 outputs in a single package
  • Performance – RMS jitter as low as 100 fs (typ)
  • Standards compliant – IEEE 1588, OTN, and SyncE
  • Programmable – I2C, SPI or OTP
  • Right size for the job – Package options from 144-BGA down to 48-QFN

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8A3xxxx Firmware Version v4.8.7 Errata Notice Errata PDF 44 KB
User Guides & Manuals
Changing 8A3xxxx Serial Port after Start-Up User Manual Manual PDF 486 KB
8A3xxxx Family Programming Guide (v4.8.7) Guide PDF 2.33 MB
8A3xxxx Firmware Version 4.8.7 Release Notes Guide PDF 101 KB
8A3xxxx Family Programming Guide (v4.8) Guide PDF 3.60 MB
ClockMatrix GUI Step-by-Step User Guide Guide PDF 4.98 MB
Application Notes & White Papers
Using a Frame or Sync Pulse Input for Clock Alignment Application Note PDF 1.57 MB
Translating Non-Integer Frequencies with ClockMatrix Application Note PDF 880 KB
Auto-Alignment of Outputs Application Note PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback Application Note PDF 155 KB
ClockMatrix EEPROM Programming Instructions Application Note PDF 550 KB
ClockMatrix Firmware Update through Serial Port and EEPROM v1.0 Application Note PDF 739 KB
AN-1033 Delay Variation Measurement and Compensation Application Note PDF 633 KB
AN-1034 Minimizing Backplane Signal Usage Application Note PDF 566 KB
AN-1031 Time Alignment Background in Wireless Infrastructure Application Note PDF 479 KB
AN-1032 Time-of-Day Within an Ideal Chassis-Based System Application Note PDF 442 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment Application Note PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy Application Note PDF 659 KB
AN-1010 ClockMatrix Time-to-Digital Converter Application Note PDF 1.63 MB
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 164 KB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.0, FWv4.8.7) Software TCP 46.94 MB
ClockMatrix Register Header Files v4.8.7 Software ZIP 278 KB
8A34003 BSDL Model Model - BSDL ZIP 2 KB
FW4.8.7 EEPROM Images and Serial Port Update Files Software ZIP 1.73 MB
8A3xxxx: How to Use SPI to Access ClockMatrix Registers Software PDF 488 KB
8A34xxx I2C-SPI Write-Read Example User Reference Software PDF 222 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 Software ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 Software ZIP 177 KB
8A340x1 BSDL Model Model - BSDL BSDL 15 KB
8A340x2 BSDL Model Model - BSDL BSDL 12 KB
ClockMatrix BGA-144 Delphi Thermal Model with 1W Power Model - Thermal PDML 3 KB
ClockMatrix BGA-144 2-Resistor Thermal Model with 1W Power Model - Thermal PDML 2 KB
ClockMatrix 48-QFN Evaluation Board Schematic Schematic PDF 199 KB
8A3x0xx Schematic Checklist (v1.22) Miscellaneous XLSX 328 KB
ClockMatrix Family Overview Overview PDF 241 KB
ClockMatrix 72-QFN (12 Output) Reference Schematic Schematic PDF 98 KB
ClockMatrix 144-BGA Devices Evaluation Board Schematic v1.1 Schematic PDF 288 KB
ClockMatrix 72-QFN (8 Output) Evaluation Board Schematic Schematic PDF 206 KB