The figure below shows a very general AC termination with the capability of externally setting Vthreshold, the receiver threshold voltage, anywhere between the ground and VCC of the receiver. This termination scheme is to be used when the clock receiver does not provide either a 50 ohm termination or a common mode threshold bias voltage. Receiver bias network element values Rpu and Rpd are shown in the table below for the most common logic families. These values center the AC swing for the receiver at the logic threshold voltage for the specified logic family. There are two other aspects in the table that bear mentioning.
1. The clock driver can be any differential driver whose differential output swing does not exceed the capabilities of the receiver nor is too small to meet the receiver minimum swing. 

2. The impedance level of the Vthreshold voltage divider is set for 2.5k. This is because some receivers, such as the IDT PClk/nPClk and IDT Clk/nClk receivers, incorporate internal pull up and pull down resistors. Setting the divider impedance level to 2.5k is typically adequate to ensure that the error in setting the threshold voltages is minimal relative to the common mode range of typical receivers.

Refer to application note AN-844 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.



Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB